Bridging Silicon Constraints with Modern Software Systems
As an undergraduate student based in Taiwan, my academic and project focus bridges the gap between low-level hardware constraints and high-level software abstractions. From designing combinational logic systems and analyzing analog op-amp circuits to building computer vision applications and developing object-oriented architectures, I enjoy engineering comprehensive solutions for complex technical challenges.
Optimizing software by understanding underlying circuit logic, memory constraints, and CPU/MCU execution cycles.
Building real-time image processing, matrix transformation, and feature extraction pipelines with OpenCV & Python.
From schematic analysis and physical sensor acquisition to structured databases and responsive user interfaces.
符致榮 · Phou Samnang
Computer Science & Information Engineering
📍 Taiwan · 🌐 Multilingual
Hardware & Circuits
Combinational logic, Op-Amps, Verilog HDL, and FPGA synthesis in Intel Quartus.
Vision & Algorithms
OpenCV image filtering, contour analysis, matrix operations, and NumPy arrays.
Award-Winning Engineering
Best Value Creation Award winner at the Vocational Cup hackathon (team "有誠意的蓮霧").
Multilingual & Adaptable
Fluent in Chinese (中文), English, and Cambodian; studying and innovating in Taiwan.
Academic & Project Milestones
CSIE Degree Focus
Taiwan Higher EducationRigorous coursework across computer architecture, object-oriented design in Java/C++, discrete mathematics, data structures, and embedded microcontroller systems.
Vocational Cup Award
Best Value Creation WinnerCollaborated under team "有誠意的蓮霧" to architect and demonstrate an end-to-end campus food waste reduction prototype with real-time tracking mechanisms.
FPGA & Circuit Synthesis
Digital Logic & QuartusHands-on experience modeling gate-level behavior, state machines, and combinational decoders using Verilog HDL on FPGA development boards.
Interested in exploring the technical projects?
Check out selected software builds, computer vision models, and engineering prototypes.